La edición 2025 de CANELOS tendrá lugar los días lunes 18 y martes 19 de agosto, de forma presencial. Serán dos días llenos de charlas plenarias técnicas y presentaciones de empresas, con participación de destacados invitados de la academia e industria microelectrónica, tanto de Chile como del extranjero. Además, se incluyen instancias de networking y un foro para cerrar el seminario discutiendo sobre el futuro de la microelectrónica en nuestro país.

Charlas plenarias

2D Materials for nanoelectronics and nanophotonics:
an R&D perspective

Francesca Iacopi

The continuous reduction trend of the electronic devices’ sizes over the past several decades has supported the growing demands for improved performance as well as for increasing multifunctionality within a smaller form -factor- as anticipated by Gordon Moore in 1965. 2D materials -nowadays a rather large class of only a few atoms thin materials-, propelled by the seminal paper on graphene by Geim and Novoselov in 2004 could further extend such trajectory. They are naturally the thinnest materials, intrinsically multifunctional, and are available as semiconductors, semimetals and insulators. 2D materials have thus ushered us quickly towards an “era of surfaces”, an uncharted territory for the semiconductor industry. Our conventional knowledge around surfaces, doping, defects and bandgap of a thin film are all challenged, and making a technological choice only based on the pristine properties of a standalone 2D material would be unwise.

After a short preamble about the use of semiconductor 2D materials such as transition metal dichalcogenides (TMDs) for advanced FETs, we will explore some exciting applications of graphene as a multifunctional, dynamically tunable semimetal. In particular, the harnessing of graphene’s properties on silicon wafers, despite inherent challenges, could deliver a broad range of miniaturized and reconfigurable functionalities to complement CMOS technologies in a system with the smallest form-factor. Over the last decade, my group pioneered an epitaxial graphene on silicon carbide on silicon technology able to fill this gap, in addition, unlocking unique functionalities for MEMS/NEMS, nano-optics and metasurfaces thanks to the specific combination of graphene with silicon carbide. This platform allows to realize any complex graphene nanopattern in a site – selective fashion, at the wafer -scale and with sufficient adhesion for subsequent integration. We will review the fundamental hallmarks of this technology and some of its most promising applications in areas as diverse as integrated energy storage, reconfigurable metasurfaces for MIR sensing and detection, and electrodes for electro-encephalography for brain-computer interfaces.

Bio: Professor Francesca Iacopi is an IEEE Fellow with over 20 years’ industrial and academic expertise in semiconductor technologies spanning interconnects, CMOS devices and packaging. Her focus is the translation of basic scientific advances in nanomaterials and novel device concepts into implementable integrated technologies. She is known for her seminal work on the integration of porous dielectrics in on-chip interconnects, and for the invention of the alloy -mediated epitaxial graphene platform on SiC on silicon wafers. She was recipient of an MRS Gold Graduate Student Award (2003), an Australian Research Council Future Fellowship (2012), a Global Innovation Award in Washington DC (2014) and was listed among the most innovative engineers by Engineers Australia (2018). Francesca serves regularly in technical and strategic committees for IEEE and the Materials Research Society. She is an Elected Member to the IEEE EDS Board of Governors (2021, 2024) and serves on the Editorial Advisory Board for ACS Applied Nanomaterials, and the IEEE The Institute magazine. She is also the inaugural Editor-in-Chief of the IEEE Trans. on Materials for Electron Devices. In 2024, she left her tenured professorship at the University of Technology Sydney to join imec USA as the inaugural Director of the Imec Indiana R&D Center based at Purdue University, IN, USA.


Trends on Nanoelectronics

The talk starts with a short presentation of Electronics and Microelectronics evolution. Then, it will be presented a set of several trends in the design of micro and nanoelectronics circuits, including architectural issues, variability and sources of variability, EDA tools, physical design issues, printability, design of transistor networks, Layout Strategies, Regularity, 3D circuits, flexible electronics, new devices, Stretchable Silicon, Fault Tolerance, Tolerance to Radiation Effects, Factory Integration, ... The talk tries to motivate the audience to explore the upcoming challenges in the field.

Bio: Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983.

Ricardo Reis

Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 750 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was a member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. He is the CASS representative at the IEEE IoT Technical Committee. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award and the 2024 Best Associate Editor of IEEE CASS Magazine. He is also Distinguished Lecturer of IEEE CEDA (2024-2025).


The Road to Gate-All-Around CMOS

Alvon Loke

Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for three years and 2nm gate-all-around SoCs anticipated late this year. Area scaling extensively driven by design/technology innovations co-optimized for primarily logic scaling continues to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the transition to the gate-all-around device architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated.

Bio: Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s gate-all-around CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. Alvin received a BASc from the University of British Columbia, and MS and PhD from Stanford. After several years in CMOS process integration, he has since worked on analog/mixed-signal design focusing on a variety of wireline links including chiplet IOs, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary and SSCS Global Chapters Chair. Alvin frequently speaks on CMOS technology and its impact on analog design, having authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS.



Workshop

Este año nuevamente se ofrecerá un workshop durante la misma semana del seminario. Pronto publicaremos más detalles y el formulario de insctripción en esta página.